Efficient implementations of quadratic digital filters

Efficient implementation structures of quadratic filters are introduced in this paper using systolic arrays, distributed arithmetic, and linear convolutions with multipliers. The implementations are based on matrix decompositions and consist of a set of parallel 1-D FIR filters in cascade with a set of sequential square-in add-out type of operations. The structures are compared using various realistic figures of merit such as data throughput delay, cost that is proportional to chip area, and variance of roundoff errors in the filter output assuming fixed-point arithmetic. For comparison purposes, the direct and Biglieri quadratic structures are included in this study. Evaluating the comparative results, the conclusion drawn is that the matrix decomposition realization of a quadratic filter implemented with systolic arrays seems to be offering the best compromise among the various conflicting figures of merit.