• DocumentCode
    1110198
  • Title

    Study of the quasi-saturation effect in VDMOS transistors

  • Author

    Darwish, Mohamed N.

  • Author_Institution
    AT&T Bell Laboratories, Reading, PA
  • Volume
    33
  • Issue
    11
  • fYear
    1986
  • fDate
    11/1/1986 12:00:00 AM
  • Firstpage
    1710
  • Lastpage
    1716
  • Abstract
    The quasi-saturation effect in VDMOS transistors is studied in detail. It is shown that such behavior is due to carrier velocity saturation in the JFET region of the device. Two-dimensional numerical simulation is carried out to study the quasi-saturation effect and its relation to different device design parameters. Experimental results over a wide range of voltage and current levels are used to verify calculated dc characteristics. In addition, the design constraint on p-body spacing in order to avoid the quasi-saturation effect is defined.
  • Keywords
    Dielectric devices; Difference equations; Finite difference methods; Impurities; Isolation technology; Numerical simulation; Poisson equations; Testing; Two dimensional displays; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1986.22732
  • Filename
    1485949
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1110198