• DocumentCode
    1110534
  • Title

    Delaunay–Voronoi Modeling of Power-Ground Planes With Source Port Correction

  • Author

    Wu, Kai-Bin ; Shiue, Guang-Hwa ; Guo, Wei-Da ; Lin, Chien-Min ; Wu, Ruey-Beei

  • Author_Institution
    Dept. of Electr. Eng. & Grad. Inst. of Commun. Eng., Nat. Taiwan Univ., Taipei
  • Volume
    31
  • Issue
    2
  • fYear
    2008
  • fDate
    5/1/2008 12:00:00 AM
  • Firstpage
    303
  • Lastpage
    310
  • Abstract
    An efficient Delaunay-Voronoi modeling of the power-ground planes suitable directly for SPICE compatibity is proposed to deal with the ground bounce noise and decoupling capacitors placement problems for the high-speed digital system designs. The model consists of virtual ports and triangular meshes with the lumped circuit elements, in which all the element values can be related to the mesh geometry shape by the analogy between the circuit equations and Maxwell´s equations. Since the analogy fails to apply due to the singular fields near the input/output pins, the via effect of driving and sensing ports is not negligible and an analytical expression from the Hankel function is thus presented for the correction term. A simple rule has been investigated for the model with minimum lumped circuit elements to accurately represent the power-ground planes over the frequency range of interests. The full-wave simulation and measurement results verify the good correlations with the proposed models for the impedance responses of regular and defective plane shapes.
  • Keywords
    Hankel transforms; Maxwell equations; SPICE; computational geometry; earthing; lumped parameter networks; mesh generation; Delaunay-Voronoi modeling; Hankel function; Maxwell equations; SPICE compatibity; circuit equations; full-wave simulation; ground bounce noise; high-speed digital system designs; impedance responses; lumped circuit elements; mesh geometry shape; power-ground planes; source port correction; triangular meshes; Delaunay triangular mesh; SPICE-compatible model; Voronoi tessellation; plane impedance; power distribution network; via effect; virtual port;
  • fLanguage
    English
  • Journal_Title
    Advanced Packaging, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1521-3323
  • Type

    jour

  • DOI
    10.1109/TADVP.2008.920326
  • Filename
    4476035