DocumentCode
1110976
Title
Error Correction in High-Speed Arithmetic
Author
Chien, Robert T. ; Hong, Se June
Author_Institution
Department of Electrical Engineering, Research Laboratory of Electronics, Massachusetts Institute of Technology
Issue
5
fYear
1972
fDate
5/1/1972 12:00:00 AM
Firstpage
433
Lastpage
438
Abstract
In high-speed multipliers, multiplication is activated by processing a group of bits in parallel. As a result, any defects in circuitry produce possible errors in positions that are separated by fixed periods. A class of codes for the correction of such iterative error patterns resulting from a single fault is presented in this paper. A decoding algorithm together with a simple implementation scheme is also discussed.
Keywords
Arithmetic codes, computer reliability, error correction in high-speed computation, error detection and correction, fault tolerant computing.; Circuit faults; Computer errors; Digital arithmetic; Error correction; Error correction codes; Fault detection; Hardware; Iterative algorithms; Iterative decoding; Redundancy; Arithmetic codes, computer reliability, error correction in high-speed computation, error detection and correction, fault tolerant computing.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1972.223538
Filename
1672131
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