• DocumentCode
    1112819
  • Title

    The Quasi-Serial Multiplier

  • Author

    Swartzlander, Earl E., Jr.

  • Author_Institution
    Hughes Aircraft Company
  • Issue
    4
  • fYear
    1973
  • fDate
    4/1/1973 12:00:00 AM
  • Firstpage
    317
  • Lastpage
    321
  • Abstract
    A novel technique for digital multiplication is presented that represents a considerable departure from conventional (i.e., add and shift or fully parallel) multiplication algorithms. The quasi-serial multiplier generates the bits of the product sequentially from least significant to most significant. Each bit is computed by "counting" the number of ones in the corresponding column of the bit-product matrix and adding the previous carrys. This single operation yields both the product bit and the carrys for the next column. The quasi-serial multiplier requires 2n of these count and add operations to determine the product of two n-bit numbers.
  • Keywords
    Current summing counters, digital multipliers, fast multipliers, full-adder counters, multiplier speed-simplicity comparison, parallel counters, quasi-serial multiplier.; Adders; Algorithm design and analysis; Application software; Computer applications; Counting circuits; Eigenvalues and eigenfunctions; Hardware; Logic arrays; Logic circuits; Logic gates; Current summing counters, digital multipliers, fast multipliers, full-adder counters, multiplier speed-simplicity comparison, parallel counters, quasi-serial multiplier.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/T-C.1973.223717
  • Filename
    1672310