DocumentCode
1115042
Title
A Note on Easily Testable Realizations for Logic Functions
Author
Kodandapani, K.L.
Author_Institution
School of Automation, Indian Institute of Science
Issue
3
fYear
1974
fDate
3/1/1974 12:00:00 AM
Firstpage
332
Lastpage
333
Abstract
It is shown that at most, n + 3 tests are required to detect any single stuck-at fault in an AND gate or a single faulty EXCLUSIVE OR (EOR) gate in a Reed-Muller canonical form realization of a switching function.
Keywords
Fault detection, Reed-Muller canonical form, stuck-at faults.; Algebra; Circuit faults; Circuit testing; Costs; Electrons; Fault detection; Logic functions; Logic testing; Switching circuits; Switching systems; Fault detection, Reed-Muller canonical form, stuck-at faults.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1974.223935
Filename
1672528
Link To Document