A 10-bit pipelined switched-current A/D converter

Author

Macq, D. ; Jespers, P.G.A.

Author_Institution

Switching Dept., Alcatel Bell Telephone, Antwerp, Belgium

Volume

29

Issue

8

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

967

Lastpage

971

Abstract

A modified RSD algorithm has been implemented in a switched-current pipelined A/D converter. The offset insensitivity of the RSD Converter reduces the effect of several nonidealities proper to current copier cells. Moreover, the benefits resulting from the large tolerances inherent to the RSD algorithm and the pipelined architecture result in an improved conversion rate. Measurements on a first prototype give an integral nonlinearity error less than 0.8 LSB for 10-bit accuracy. Power dissipation is 20 mW and silicon area is 2.5 mm². The measured sampling rate is 550 kS/s. It is an improvement by a factor of twenty compared to known equivalent CMOS switched-current converters. It is nevertheless still well below the predicted conversion rate of 4.5 MHz, which should be obtained once this A/D converter is integrated into an analog front-end. Full compatibility with standard digital technologies makes this kind of converter attractive for low power, medium-fast converters with 10-bit accuracy

Keywords

CMOS integrated circuits; analogue-digital conversion; linear integrated circuits; pipeline processing; switched networks; 20 mW; CMOS; RSD algorithm; analog front-end; conversion rate; integral nonlinearity error; medium-fast converters; offset insensitivity; pipelined switched-current A/D converter; power dissipation; sampling rate; CMOS technology; Capacitance; Helium; Power dissipation; Prototypes; Sampling methods; Silicon; Switching circuits; Switching converters; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.297705

Filename

297705