Steamroller Module and Adaptive Clocking System in 28 nm CMOS

Author

Wilcox, Kathryn ; Cole, Robert ; Fair, Harry R. ; Gillespie, Kevin ; Grenat, Aaron ; Henrion, Carson ; Jotwani, Ravi ; Kosonocky, Stephen ; Munger, Benjamin ; Naffziger, Samuel ; Orefice, Robert S. ; Pant, Sanjay ; Priore, Donald A. ; Rachala, Ravinder ;

Author_Institution

Adv. Micro Devices, Boxborough, MA, USA

Volume

50

Issue

1

fYear

2015

fDate

Jan. 2015

Firstpage

24

Lastpage

34

Abstract

This work describes the physical design implementation of the AMD “Steamroller” module and adaptive clocking system that are both integral pieces of the AMD Kaveri APU SoC which was implemented using a 28 nm high-K metal gate Bulk CMOS process. The Steamroller module occupies 29.47 mm ² and contains 236 million transistors. Various aspects of the core design are covered including the power and timing methodologies as well as design challenges moving from 32 nm SOI to 28 nm Bulk CMOS. Adaptive clocking, one of the key features used for core power efficiency, is described in detail.

Keywords

CMOS digital integrated circuits; clocks; high-k dielectric thin films; system-on-chip; AMD Kaveri APU SoC; AMD Steamroller module; adaptive clocking system; core power efficiency; high-k metal gate bulk CMOS process; power methodology; size 32 nm to 28 nm; timing methodology; Clocks; Delays; Detectors; Latches; Logic gates; Metals; 28 nm CMOS; flip-flops; high-frequency CMOS design; microprocessors; power efficiency;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2014.2357428

Filename

6926864