• DocumentCode
    1121581
  • Title

    Fully implanted InP JFET with an abrupt p+-n junction

  • Author

    Cheng, Chu-Liang ; Wang, Kou-Wei ; Parker, Sandra M.

  • Author_Institution
    AT&T Bell Laboratories, Murray Hill, NJ
  • Volume
    8
  • Issue
    10
  • fYear
    1987
  • fDate
    10/1/1987 12:00:00 AM
  • Firstpage
    483
  • Lastpage
    485
  • Abstract
    We report the first fully implanted InP junction field-effect transistor (JFET) with an abrupt p+-n junction. The device was made on a semi-insulating InP substrate with Si++implant for the n-channel and Be/P co-implant for the p+-region. A novel self-aligned process was used to reduce the gate-source spacing and thus minimize the series resistance. Good pinch-off characteristics and very low gate leakage current were obtained. The extrinsic transconductance is approximately 40 mS/mm for a gate length of 5 µm and a channel doping of 6 × 1016/cm3.
  • Keywords
    Doping; Etching; FETs; Fabrication; Implants; Indium gallium arsenide; Indium phosphide; Leakage current; Temperature; Transconductance;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/EDL.1987.26702
  • Filename
    1487252
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1121581