Post-Layout Simulation Time Reduction for Phase-Locked Loop Frequency Synthesizer Using System Identification Techniques

Author

Lechang Liu ; Pokharel, R.

Author_Institution

Kyushu Univ., Fukuoka, Japan

Volume

33

Issue

11

fYear

2014

fDate

Nov. 2014

Firstpage

1751

Lastpage

1755

Abstract

Compact model extraction of phase-locked loop (PLL) frequency synthesizer using system identification techniques is proposed to reduce post-layout simulation time. This is the first published compact model for PLL using system identification techniques. It features an autoregressive exogenous model for the charge pump and the loop filter with a lookup table for nonlinearity compensation and a radial basis function neural network for the voltage-controlled oscillator with nonlinear frequency-voltage relationship, thereby reducing the post-layout simulation time to 26% of the original circuits with the accuracy of 93%.

Keywords

autoregressive processes; electronic engineering computing; frequency synthesizers; phase locked loops; radial basis function networks; PLL frequency synthesizer; autoregressive exogenous model; charge pump; compact model extraction; lookup table; loop filter; nonlinear frequency-voltage relationship; nonlinearity compensation; phase-locked loop frequency synthesizer; post-layout simulation time reduction; radial basis function neural network; system identification technique; voltage-controlled oscillator; Charge pumps; Computational modeling; Frequency conversion; Integrated circuit modeling; Phase locked loops; Voltage control; Voltage-controlled oscillators; Autoregressive exogenous model (ARX); compact model; neural network; phase-locked loop; system identification;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2014.2354291

Filename

6926919