DocumentCode
112423
Title
A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems
Author
Yi Wang ; Min Huang ; Zili Shao ; Chan, Henry ; Bathen, L.A.D. ; Dutt, N.D.
Author_Institution
Guangdong Province Key Lab. of Popular High Performance Comput., Shenzhen Univ., Shenzhen, China
Volume
33
Issue
11
fYear
2014
fDate
Nov. 2014
Firstpage
1623
Lastpage
1631
Abstract
The increasing density of NAND flash memory leads to a dramatic increase in the bit error rate of flash, which greatly reduces the ability of error correcting codes (ECC) to handle multibit errors. NAND flash memory is normally used to store the file system metadata and page mapping information. Thus, a broken physical page containing metadata may cause an unintended and severe change in functionality of the entire flash. This paper presents Meta-Cure, a novel hardware and file system interface that transparently protects metadata in the presence of multibit faults. Meta-Cure exploits built-in ECC and replication in order to protect pages containing critical data, such as file system metadata. Redundant pairs are formed at run time and distributed to different physical pages to protect against failures. Meta-Cure requires no changes to the file system, on-chip hierarchy, or hardware implementation of flash memory chip. We evaluate Meta-Cure under a real-embedded platform using a variety of I/O traces. The evaluation platform adopts dual ARM Cortex A9 processor cores with 64 Gb NAND flash memory. We have evaluated the effectiveness of Meta-Cure on the new technology file system file system. Experimental results show that the proposed technique can reduce uncorrectable page errors by 70.38% with less than 7.86% time overhead in comparison with conventional error correction techniques.
Keywords
NAND circuits; error correction codes; error statistics; flash memories; integrated circuit reliability; integrated memory circuits; meta data; Meta-Cure; NAND flash memory storage systems; bit error rate; dual ARM Cortex A9 processor cores; error correcting codes; error correction techniques; file system metadata; hardware-file system interface; reliability-aware address mapping strategy; Ash; Bit error rate; Error correction; Error correction codes; Hardware; Reliability; Error correcting codes (ECC); NAND flash memory; memory management; metadata; redundancy; reliability;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2014.2347929
Filename
6926929
Link To Document