Pulsewidth-Modulated Z-Source Neutral-Point-Clamped Inverter

This paper presents the careful integration of a newly proposed Z-source topological concept to the basic neutral-point-clamped (NPC) inverter topology for designing a three-level inverter with both voltage-buck and voltage-boost capabilities. The designed Z-source NPC inverter uses two unique X-shaped inductance-capacitance (LC) impedance networks that are connected between two isolated dc input power sources and its inverter circuitry for boosting its AC output voltage. Through the design of an appropriate pulsewidth-modulation (PWM) algorithm, the two impedance networks can be short-circuited sequentially (without shooting through the inverter full DC link) for implementing the ldquonearest-three-vectorrdquo modulation principle with minimized harmonic distortion and device commutations per half carrier cycle while performing voltage boosting. With only a slight modification to the inverter PWM algorithm and by short-circuiting the two impedance networks simultaneously, the designed NPC inverter, with no requirement for deadtime delay, can also be operated with a completely eliminated common-mode voltage. Implementation wise, a detailed vectorial analysis interestingly shows that the same generic set of carrier-based modulation expressions can be used for controlling the -source two-level inverter and NPC inverter with and without reduced common-mode switching. All findings presented in this paper have been confirmed in simulation and experimentally using an implemented laboratory prototype.