Comprehensive Analysis of Random Telegraph Noise Instability and Its Scaling in Deca–Nanometer Flash Memories

Author

Ghetti, Andrea ; Compagnoni, Christian Monzio ; Spinelli, Alessandro S. ; Visconti, Angelo

Author_Institution

Numonyx, R&D-Technol. Dev., Agrate Brianza, Italy

Volume

56

Issue

8

fYear

2009

Firstpage

1746

Lastpage

1752

Abstract

This paper presents a comprehensive investigation of random telegraph noise (RTN) in deca-nanometer Flash memories, considering both the nor and the nand architecture. The statistical distribution of the threshold voltage instability is analyzed in detail, evidencing that the slope of its exponential tails is the critical parameter determining the scaling trend for RTN. By means of 3-D TCAD simulations, the slope is shown to be the result of cell geometry, atomistic substrate doping, and random placement of traps over the cell active area. Finally, the slope dependence on cell geometry (width, length, and oxide thickness), doping, and bias conditions is summarized in a powerful formula that is able to predict the RTN instabilities in deca-nanometer Flash memories.

Keywords

NAND circuits; NOR circuits; circuit noise; flash memories; random noise; statistical analysis; technology CAD (electronics); 3-D TCAD simulations; NAND architecture; NOR architecture; atomistic substrate doping; cell geometry; deca-nanometer flash memories; random telegraph noise instability; statistical distribution; threshold voltage instability; trap random placement; Electron traps; Flash memory; Geometry; Nonvolatile memory; Probability distribution; Semiconductor device noise; Solid modeling; Statistical distributions; Substrates; Telegraphy; Threshold voltage; Flash memories; random telegraph noise (RTN); semiconductor device modeling; threshold voltage instability;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2009.2024031

Filename

5159507