Noise Prediction for Rate Multiplier and Binary Adder Frequency Synthesizers

The theory for design of a rate multiplier or a binary adder frequency synthesizer for a specified level of noise attenuation is developed. Examples are presented to demonstrate the design procedure and the pattern of the pulse train output. The phase jitter associated with each pulse is characterized and illustrated in the time domain. The maximum absolute phase deviation is used as a measure of the phase modulation amplitude of the pulse train. Computer simulation resulted in simple equations approximating the amplitude of worst case spectral components.