Efficient Decoder Architecture for Single Block-Row Quasi-Cyclic LDPC Codes

Single block-row quasi-cyclic low-density parity-check codes have been proposed for high-speed applications recently. However, no existing work has systematically addressed the decoder design issue for such kind of codes. In this brief, an efficient decoder architecture for such kinds of codes is proposed by exploring the geometry properties of the check matrix. Compared with conventional approaches, the proposed method can achieve more than 20.8% of memory reduction. Additionally, the subblock-sharing technique and the suboptimal low-latency searching method are employed to further reduce the hardware complexity.