Experimental Demonstration of Concatenated LDPC and RS Codes by FPGAs Emulation

Author

Mizuochi, Takashi ; Konishi, Yoshiaki ; Miyata, Yoshikuni ; Inoue, Tomoka ; Onohara, Kiyoshi ; Kametani, Soichiro ; Sugihara, Takashi ; Kubo, Kazuo ; Yoshida, Hideo ; Kobayashi, Tatsuya ; Ichikawa, Toshiyuki

Author_Institution

Mitsubishi Electr. Corp., Kamakura, Japan

Volume

21

Issue

18

fYear

2009

Firstpage

1302

Lastpage

1304

Abstract

The concatenation of low-density parity-check and Reed-Solomon codes for forward error correction has been experimentally demonstrated for the first time in this letter. Using a 2-bit soft-decision large-scale integration and high-speed field-programmable gate arrays, a net coding gain of 9.0 dB was achieved with 20.5% redundancy with four iterative decoding for an input bit-error rate of 8.9 times 10^-3 at 31.3 Gb/s.

Keywords

Reed-Solomon codes; concatenated codes; error statistics; field programmable gate arrays; forward error correction; iterative decoding; parity check codes; 2-bit soft-decision large-scale integration; FPGA; LDPC codes; RS codes; Reed-Solomon code; bit rate 31.3 Gbit/s; bit-error rate; forward error correction; gain 9.0 dB; iterative decoding; low-density parity-check code; Concatenated coding; Reed–Solomon (RS) codes; field-programmable gate arrays (FPGAs); forward error correction (FEC); optical communication;

fLanguage

English

Journal_Title

Photonics Technology Letters, IEEE

Publisher

ieee

ISSN

1041-1135

Type

jour

DOI

10.1109/LPT.2009.2025867

Filename

5161312