• DocumentCode
    1133327
  • Title

    A Graph Model for Fault-Tolerant Computing Systems

  • Author

    Hayes, John P.

  • Author_Institution
    Department of Electrical Engineering and the Computer Science Program, University of Southern California
  • Issue
    9
  • fYear
    1976
  • Firstpage
    875
  • Lastpage
    884
  • Abstract
    An approach to fault-tolerant design is described in which a computing system S and an algorithm A to be executed by S are both defined by graphs whose nodes represent computing facilities. A is executable by S if A is isomorphic to a subgraph of S.A k-fault is the removal of k nodes (facilities) from S.S is a k-fault tolerant (k-FT) realization of A if A can be executed by S with any k-fault present in S. The problem of designing optimal k-FT systems is considered where A is equated to a 0-FT system. Techniques are described for designing optimal k-FT realizations of single-loop systems; these techniques are related to results in Hamiltonian graph theory. The design of optimal k-FT realizations of certain types of tree systems is also examined. The advantages and disadvantages of the graph model are discussed.
  • Keywords
    Computer architecture, fault-tolerant computing, fault-tolerant design, graph theory, Hamiltonian graphs, single-loop systems, tree systems.; Algorithm design and analysis; Circuit faults; Computer architecture; Computer displays; Computer errors; Fault tolerance; Fault tolerant systems; Graph theory; Hardware; Tree graphs; Computer architecture, fault-tolerant computing, fault-tolerant design, graph theory, Hamiltonian graphs, single-loop systems, tree systems.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1976.1674712
  • Filename
    1674712