A 54×54-b regularly structured tree multiplier

Author

Goto, Gensuke ; Sato, Tomio ; Nakajima, Masao ; Sukemura, Takao

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

Volume

27

Issue

9

fYear

1992

fDate

9/1/1992 12:00:00 AM

Firstpage

1229

Lastpage

1236

Abstract

A 54-b×54-b parallel multiplier was implemented in 0.88-μm CMOS using the new, regularly structured tree (RST) design approach. The circuit is basically a Wallace tree, but the tree and the set of partial-product-bit generators are combined into a recurring block which generates seven partial-product bits and compresses them to a pair of bits for the sum and carry signals. This block is used repeatedly to construct an RST block in which even wiring among blocks included in wire shifters is designed as recurring units. By using recurring wire shifters, the authors can expand the level of repeated blocks to cover the entire adder tree, which simplifies the complicated Wallace tree wiring scheme. In addition, to design time savings, layout density is increased by 70% to 6400 transistors/mm², and the multiplication time is decreased by 30% to 13 ns

Keywords

CMOS integrated circuits; digital arithmetic; integrated logic circuits; multiplying circuits; 0.88 micron; 13 ns; CMOS; Wallace tree; layout density; partial-product-bit generators; recurring block; recurring wire shifters; regularly structured tree multiplier; Adders; Arithmetic; Compressors; Computer architecture; Counting circuits; Hardware; Microprocessors; VLIW; Very large scale integration; Wiring;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.149426

Filename

149426