DocumentCode
1136354
Title
An Algorithm for Optimal NAND Cascade Logic Synthesis
Author
Papachristou, Christos A.
Author_Institution
Department of Electrical Engineering, Drexel University
Issue
12
fYear
1978
Firstpage
1099
Lastpage
1111
Abstract
This paper is concerned with optimal synthesis of switching logic by a limited depth tree-like network, the NAND cascade. This cascade consists of a number of complete three-level, fan-in restricted NAND trees feeding a NAND collector. The goal of the proposed synthesis is to minimize the number of NAND trees of the cascade, which in turn will minimize its overall depth, i.e., the delay time of the cascade.
Keywords
Combinational logic; NAND cascade; NAND collector; NAND gates; NAND tree formula; NAND trees; switching functions; Catalogs; Circuit synthesis; Delay effects; Integrated circuit synthesis; Integrated circuit technology; Logic design; Logic gates; Network synthesis; Network topology; Switching circuits; Combinational logic; NAND cascade; NAND collector; NAND gates; NAND tree formula; NAND trees; switching functions;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1978.1675012
Filename
1675012
Link To Document