DocumentCode
1140115
Title
Energy control and accurate delay estimation in the design of CMOS buffers
Author
Ma, Sha ; Franzon, Paul
Author_Institution
Sun Microsyst. Comput. Corp., Sunnyvale, CA, USA
Volume
29
Issue
9
fYear
1994
fDate
9/1/1994 12:00:00 AM
Firstpage
1150
Lastpage
1153
Abstract
The purpose of this paper is to present a computer aided method to design CMOS multistage variable-taper buffers with optimum energy efficiencies while satisfying speed requirements. The resulting designs typically save at least 20-30% energy per computation over conventionally designed circuits with the same speed. We also present a technique for obtaining accurate empirical delay equations for buffers
Keywords
CMOS integrated circuits; VLSI; array signal processing; buffer circuits; circuit CAD; power consumption; power control; CMOS buffer design; CMOS multistage variable-taper buffers; accurate delay estimation; accurate empirical delay equations; computer aided method; energy control; optimum energy efficiencies; speed requirements; Batteries; Circuits; Delay estimation; Design methodology; Energy consumption; Energy efficiency; Equations; Inverters; Parasitic capacitance; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.309914
Filename
309914
Link To Document