DocumentCode
1140286
Title
Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design
Author
Singhee, Amith ; Rutenbar, Rob A.
Author_Institution
IBM T J. Watson Res. Center, Yorktown Heights, NY, USA
Volume
28
Issue
8
fYear
2009
Firstpage
1176
Lastpage
1189
Abstract
Circuit reliability under random parametric variation is an area of growing concern. For highly replicated circuits, e.g., static random access memories (SRAMs), a rare statistical event for one circuit may induce a not-so-rare system failure. Existing techniques perform poorly when tasked to generate both efficient sampling and sound statistics for these rare events. Statistical blockade is a novel Monte Carlo technique that allows us to efficiently filter-to block-unwanted samples that are insufficiently rare in the tail distributions we seek. The method synthesizes ideas from data mining and extreme value theory and, for the challenging application of SRAM yield analysis, shows speedups of 10 - 100 times over standard Monte Carlo.
Keywords
Monte Carlo methods; SRAM chips; integrated circuit design; Monte Carlo technique; circuit reliability; memory design; random parametric variation; rare circuit events; static random access memories; statistical blockade; very fast statistical simulation; Design automation; Monte Carlo methods; extreme values; memories; simulation; statistics; yield estimation;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2009.2020721
Filename
5166555
Link To Document