NVP: Non-uniform voltage and pulse width settings for power efficient hybrid STT-RAM

As technology scales down, the leakage power of SRAM based cache becomes a more critical source of power dissipation, particularly for large last level cache where leakage power is dominant. The emerging non-volatile spin transfer torque RAM (STT-RAM) is a candidate to substitute SRAM due to its low leakage power and high thermal stability. However, considerable high energy and long latency of write operations in STT-RAMs are barriers to their commercial adoption. To address this problem, we propose a hybrid non-uniform cache architecture (NUCA) by combining SRAMs and STT-RAMs with different operating voltage/pulse width settings. Operating at low voltage increases the probability of failure. To alleviate this, we propose a technique that reduces STT-RAM write access energy by lowering voltage while ensures correctness by either retrying the failed writes or increasing effective pulse width. Simulation results indicate overall 20-30% power gain for various workloads in hybrid cache architecture. This comes with less than 2% performance loss.