Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications

Charge coupled device (CCD) memory technology offers potential economic advantages over semiconductor random-access memory technology. However, the limitations incurred by the serial nature of CCD´s have previously restricted their application to computer mainframe memories. The 64 kbyte CCD memory system described in this paper demonstrates the feasibility of CCD memory technology for moderate size memory systems applicable to microcomputer systems. Design objectives included low cost, adequate performance, reliable operation, small size, and low power consumption as well as simple interfacing to standard microprocessors. A simple two-level organization employing a random access memory (RAM) to buffer the serial CCD memory was used to improve the memory system performance and to simplify the interfacing of microcomputers. It is anticipated that the memory system can be easily modified to use 64 kbit and larger CCD memory devices as these become available. Further more, the memory system control logic could be integrated on a single large-scale integration (LSI) chip, thereby facilitating the fabrication of relatively large and economical memory systems with a low component count.