Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders

Parallel counters are multiple input circuits that count the number of their inputs that are in a given state. In this correspondence, the implementation of pipelined binary parallel counters with networks of latched quaternary threshold logic full adders is described and compared with the implementation using networks of latched binary full adders. Since each signal variable in quaternary logic may assume four logical states, twice the informational content of a binary variable, an over 50 percent savings in the total number of intermediate signal variables required to implement the parallel counter results. With the new quaternary logic circuits we will employ, over 40 percent fewer transistors and resistors are necessary for the implementation of pipelined binary parallel counters. The combination of these two factors could provide significantly reduced die areas for integrated pipelined parallel counters.