DocumentCode
1142145
Title
Comprehensive Approach to High-Performance Server Chipset Debug
Author
Parulkar, Ishwar ; Turumella, Babu
Author_Institution
Sun Microsyst., Santa Clara, CA, USA
Volume
26
Issue
3
fYear
2009
Firstpage
70
Lastpage
77
Abstract
This article describes a comprehensive approach for silicon debug of a server chipset that includes a high-performance, third-generation chip-multithreaded (CMT) Sparc microprocessor. Efficiently debugging the chipset required a combination of debug features in silicon and system platforms, firmware support for debug, test generation tools, and debug data interpretation tools. Several useful lessons were learned in the process.
Keywords
automatic test software; firmware; microprocessor chips; debug data interpretation tools; firmware support; server chipset debug; test generation tools; third-generation chip-multithreaded microprocessor; Application specific integrated circuits; Computer bugs; Error correction; Geometry; Hardware; Microprocessors; Silicon; Sun; System testing; Yarn; CMT Sparc microprocessor; RAS; SerDes; debug; design and test; multithreaded processors; server chipset; test generation; verification;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2009.53
Filename
5167509
Link To Document