Characterization of STI Edge Effects on CMOS Variability

Layout effects (well proximity effect, gate-STI distance effect, litho proximity effects, etc.) can lead to significant deviations between measured and modeled drain currents in advanced CMOS processes. Because several of these effects can occur at the same time and because a proper distinction between systematic and random effects is not always made, this often leads to confusion on the subject of variability. Using a dedicated set of-asymmetrically designed-matched pair test structures and a data analysis technique based on so-called mismatch sweeps, we answer some important questions in these discussions on variability in advanced CMOS technologies. Taking the STI-induced stress effect as an example, we show that, although there can be a large systematic offset in drain current and threshold voltage due to this effect, there is no significant impact on random mismatch fluctuations.