Optimal retiming of level-clocked circuits using symmetric clock schedules

Using level-sensitive latches instead of edge-triggered registers for storage elements in a synchronous system can lead to faster and less expensive circuit implementations. These advantages derive from an increased flexibility in scheduling the computations to be performed. In edge-clocked circuits, the amount of time available for the computation between two registers is precisely the length of the clock cycle, while in level-clocked circuits computations can borrow time across latches, potentially reducing the amount of dead time not used for computation. In either type of circuit, maximizing performance requires locating the storage elements to spread the computation uniformly across a number of clock cycles. Retiming is the process of rearranging the storage elements in a circuit to reduce its cycle time or number of storage elements without changing its functionality. In this paper, we extend the retiming techniques developed by Leiserson, Rose, and Saxe (1983, 1991) for edge-clocked circuits to a general class of multi-phase, level-clocked circuits controlled using symmetric clock schedules. We first define correct timing for level-clocked circuits and describe the set of timing constraints that must be satisfied. We then present an efficient algorithm for generating and solving a set of retiming constraints at a particular clock period that results in a retimed circuit satisfying the timing constraints (if any such circuit exists). The minimum clock period for which there is a valid retiming can then be determined using a binary search