A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps

Author

Kuo, Chien-Hung ; Liu, Shen-Iuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

39

Issue

11

fYear

2004

Firstpage

2041

Lastpage

2045

Abstract

A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25-μm 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is -65 dBc below the desired signal.

Keywords

CMOS integrated circuits; MIM devices; band-pass filters; capacitors; delta-sigma modulation; integrated circuit design; low-power electronics; operational amplifiers; 0.25 micron; 1 V; 10.7 MHz; 1P5M CMOS process; 200 kHz; 7.13 MHz; 8.45 mW; MIM capacitors; double-sampling techniques; fourth-order bandpass ΔΣ modulators; image tone; in-band third-order intermodulation distortion; sampling frequency; switched op amps; Bandwidth; CMOS process; Clocks; Delta modulation; Dynamic range; Energy consumption; Frequency; MIM capacitors; Operational amplifiers; Sampling methods;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2004.835792

Filename

1347335