DocumentCode
1145979
Title
A Regular Layout for Parallel Adders
Author
Brent, Richard P. ; Kung, H.T.
Author_Institution
Department of Computer Science, Australian National University
Issue
3
fYear
1982
fDate
3/1/1982 12:00:00 AM
Firstpage
260
Lastpage
264
Abstract
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
Keywords
Addition; VLSI; area-time complexity; carry lookahead; circuit design; combinational logic; models of computation; parallel addition; parallel polynomial evaluation; prefix computation; Adders; Area measurement; Capacitance; Computational modeling; Computer science; Concurrent computing; Costs; Joining processes; Very large scale integration; Wire; Addition; VLSI; area-time complexity; carry lookahead; circuit design; combinational logic; models of computation; parallel addition; parallel polynomial evaluation; prefix computation;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1982.1675982
Filename
1675982
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