DocumentCode
1146798
Title
Extraction of defect size distributions in an IC layer using test structure data
Author
Khare, Jitendra B. ; Maly, Wojciech ; Thomas, Michael E.
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Volume
7
Issue
3
fYear
1994
fDate
8/1/1994 12:00:00 AM
Firstpage
354
Lastpage
368
Abstract
This paper demonstrates the need for specialized test structures and algorithms to obtain defect characteristics which are necessary for accurate yield prediction. Using one such specialized test structure, a general methodology for extracting size distribution parameters for both shorts and opens in any IC layer, which is independent of defect and yield models, is developed in this paper. The application of this methodology is illustrated by means of a fabrication experiment
Keywords
integrated circuit manufacture; integrated circuit testing; production testing; statistical analysis; IC layer; defect size distributions; fabrication; opens; shorts; test structure data; yield prediction; Circuit faults; Contamination; Data mining; Fabrication; Helium; Integrated circuit modeling; Integrated circuit testing; Manufacturing; Modems; Terminology;
fLanguage
English
Journal_Title
Semiconductor Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
0894-6507
Type
jour
DOI
10.1109/66.311339
Filename
311339
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