psub guard ring design and modeling for the purpose of substrate noise isolation in the SOC era

Author

Hsu, Tsun-Lai ; Chen, Yu-Chia ; Tseng, Hua-Chou ; Liang, Victor ; Jan, Jin Shyong

Author_Institution

Central R&D Div., United Microelectron. Corp., Hsinchu, Taiwan

Volume

26

Issue

9

fYear

2005

Firstpage

693

Lastpage

695

Abstract

This letter reports the effect of using a p-minus substrate guard ring (psub GR) structure to reduce substrate noise coupling. A corresponding equivalent lump circuit model that predicts the substrate noise isolation behavior of this structure versus distance is also presented. For this particular study, it was found that integrating the psub GR into conventional GR designs can improve substrate noise isolation capabilities of conventional p+ guard rings and n-well guard rings by -15 dB and -5 dB, respectively. This scheme requires no extra masks or processes, and no special substrate material.

Keywords

equivalent circuits; interference suppression; substrates; system-on-chip; 15 dB; 5 dB; SOC; equivalent lump circuit model; n-well guard ring; p+ guard ring; p-minus substrate guard ring; psub guard ring design; substrate noise coupling; substrate noise isolation; CMOS technology; Circuit noise; Costs; Coupling circuits; Frequency; Implants; Noise measurement; Noise reduction; Semiconductor device modeling; Working environment noise; Lump circuit model; n-well guard ring; p-minus substrate guard ring; p-plus guard ring (psub GR); substrate noise isolation;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2005.854351

Filename

1499002