Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices

Author

Mori, Seiichi ; Araki, Yoshiko Yamaguchi ; Sato, Muneharu ; Meguro, Hisataka ; Tsunoda, Hiroaki ; Kamiya, Eiji ; Yoshikawa, Kuniyoshi ; Arai, Norihisa ; Sakagami, Eiji

Author_Institution

Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan

Volume

43

Issue

1

fYear

1996

fDate

1/1/1996 12:00:00 AM

Firstpage

47

Lastpage

53

Abstract

This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule

Keywords

EPROM; MOS memory circuits; VLSI; cellular arrays; dielectric thin films; 0.25 micron; 3 to 13 nm; MOS process; ONO interpoly dielectric; charge retention capability; flash memory devices; memory cell transistors; nonvolatile memory devices; quarter-micron design rule; stacked-gate structure; thickness scaling limitation factors; threshold voltage stability; Degradation; Dielectric devices; Dielectric substrates; Flash memory; Nonvolatile memory; Semiconductor films; Silicon compounds; Stability; Testing; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.477592

Filename

477592