DocumentCode
1147606
Title
Delayed-Staging Hierarchy Optimization
Author
Silberman, Gabriel M.
Author_Institution
IBM Thomas J. Watson Research Center
Issue
11
fYear
1983
Firstpage
1029
Lastpage
1037
Abstract
A geometric programming model is developed to optimize delayed-staging (DS) storage hierarchies. These hierarchies have direct paths between the CPU and the k fastest storage levels (k = 1 in a linear hierarchy), allowing for some concurrency in the flow of data through the hierarchy. The criterion for optimization is the minimization of average hierarchy access time subject to budgetary limitations, given the cache access time and the backing-store capacity.
Keywords
Average access time; delayed-staging; geometric programming; miss ratios; storage hierarchies; Cache storage; Central Processing Unit; Computer science; Concurrent computing; Constraint optimization; Cost function; Delay effects; Linear programming; Parallel processing; Solid modeling; Average access time; delayed-staging; geometric programming; miss ratios; storage hierarchies;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1983.1676153
Filename
1676153
Link To Document