Impact of a vertical Φ-shape transistor (VΦT) cell for 1 Gbit DRAM and beyond

We propose a vertical Φ-shape transistor (VΦT) cell for 1 Gbit DRAM and beyond. The VΦT is a vertical MOSFET whose gate surrounds its channel region like a Greek-alphabetic letter Φ, fabricated through the penetration of the gate electrode (=word line) which has been formed beforehand, and the formation of the channel plug inside the penetrating hole. The VΦT provides the 4F² cell. The substantial simplicity of the VΦT process contributes to the reduction in the number of process steps. The above two features result in the drastic reduction in total chip cost. Moreover, we demonstrate that the advantages on electrical properties of the VΦT become more prominent with proceeding of scaling down. We have indicated that the VΦT is a promising candidate for the gigabit DRAM in terms of size, cost, and performance