DocumentCode
1152698
Title
A Signed Bit-Sequential Multiplier
Author
Rhyne, Tom ; Strader, Noel R., II
Author_Institution
MCC
Issue
10
fYear
1986
Firstpage
896
Lastpage
901
Abstract
Bit-sequential algorithms for arithmetic processing are good candidates for VLSI signal processing circuits because of their canonical structure and minimal interconnection requirements. Several recent papers have dealt with algorithms that accept unsigned binary inputs, one bit at a time, least significant bit first, and produce an unsigned binary product in a bit-serial fashion.
Keywords
Bit-sequential multiplication; Booth´s algorithm; VLSI signal processing circuits; carry-save arithmetic; computer arithmetic; Clocks; Digital arithmetic; Hardware; Integrated circuit interconnections; Signal processing algorithms; Very large scale integration; Bit-sequential multiplication; Booth´s algorithm; VLSI signal processing circuits; carry-save arithmetic; computer arithmetic;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1986.1676680
Filename
1676680
Link To Document