DocumentCode
1153352
Title
Mapping Homogeneous Graphs on Linear Arrays
Author
Ramakrishnan, I.V. ; Fussell, D.S. ; Silberschatz, Abraham
Author_Institution
Department of Computer Science, State University of New York
Issue
3
fYear
1986
fDate
3/1/1986 12:00:00 AM
Firstpage
189
Lastpage
209
Abstract
This paper presents a formal model of linear array processors suitable for VLSI implementation as well as graph representations of programs suitable for execution on such a model. A distinction is made between correct mapping and correct execution of such graphs on this model and the structure of correctly mappable graphs are examined. The formalism developed is used to synthesize algorithms for this model.
Keywords
Array processors; VLSI; graphs; mapping; parallel processing; synthesis; Application software; Bandwidth; Computer aided instruction; Computer architecture; Computer peripherals; Computer science; Data mining; Parallel processing; Systolic arrays; Very large scale integration; Array processors; VLSI; graphs; mapping; parallel processing; synthesis;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1986.1676744
Filename
1676744
Link To Document