EMC Assessment at Chip and PCB Level: Use of the ICEM Model for Jitter Analysis in an Integrated PLL

This paper deals with the use of the integrated circuit electromagnetic model (ICEM) to analyze, predict, and optimize autocompatibility and electromagnetic emission at chip and system level. ICEM is currently under standardization process (IEC62014-3). The basic ICEM architecture is composed of a power distribution network model and an internal current source modeling digital activity. Such an approach enables the description of any kind of digital or mixed-signal design. This model is useful either for the IC manufacturer or the system manufacturer. The power distribution network of a printed circuit board (PCB) can be optimized using this model by choosing the number and the right values of decoupling capacitors as well as the size of power planes. The IC manufacturer may check out the autocompatibility of an IC and determine the number of power pins as well as the package to be used. As an example, jitter analysis of an integrated phase-locked-loop can be performed using ICEM. This paper demonstrates that this jitter can be predicted by simulation and that corrective solutions can be provided and checked out before implementation