Design and implementation of an embedded 512-KB level-2 cache subsystem

Author

Shin, Jinuk Luke ; Petrick, Bruce ; Singh, Mandeep ; Leon, Ana Sonia

Author_Institution

Sun Microsystems Inc., Sunnyvale, CA, USA

Volume

40

Issue

9

fYear

2005

Firstpage

1815

Lastpage

1820

Abstract

Dual on-chip 512-KB unified second level (L2) caches for an UltraSparc processor are implemented using 0.13-μm technology. Each 512-KB unit is implemented using 34 million transistors to achieve 1.4 GHz and 2.6 W at 1.3 V and 85°C. This fully integrated subsystem is composed of conventional data and tag SRAMs along with datapaths, controller, and test engines. The unit achieves one of the shortest on-chip L2 cache latencies reported for 64-bit microprocessors, with a data latency of only four cycles including ECC correction for 128-bit data. In addition, balanced custom and automated design methodologies are used to achieve the aggressive design cycle. Architectural and physical design solutions to build this integrated short latency L2 cache are discussed.

Keywords

SRAM chips; cache storage; microprocessor chips; 0.13 micron; 1.3 V; 1.4 GHz; 2.6 W; 512 KB; 85 C; ECC correction; SRAM; UltraSparc processor; automated design; cache latency; coupling noise; current-mode sense amplifier; custom design; data latency; deep-submicron CMOS technology; integrated subsystem; microprocessors; second level caches; CMOS technology; Clocks; Delay; Design methodology; Frequency; Logic; Microprocessors; Random access memory; Silicon; Testing; Coupling noise; ECC; SRAM; UltraSPARC; current-mode sense amplifier; deep-submicron CMOS technology; microprocessor; on-chip L2 cache;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.852165

Filename

1501979