Integer Division in Linear Time with Bounded Fan-In

Author

Purdy, Carla Neaderhouser ; Purdy, George B.

Author_Institution

Department of Computer Science, University of Cincinnati

Issue

5

fYear

1987

fDate

5/1/1987 12:00:00 AM

Firstpage

640

Lastpage

644

Abstract

A binary algorithm for division of an (M + N)-bit integer by an N-bit integer is presented. The algorithm produces the (M + 1)-bit quotient and the N-bit remainder in time O(M + N). Two hardware implementations, one using combinational logic in cellular arrays, and one employing systolic arrays, are given. These implementations are designed for modularity and regularity, and thus are suitable for VLSI systems. An important property of these implementations is that decisions are based on only one bit of the operands. Thus, fan-in and length of connecting wires are bounded independently of operand size. In addition, the systolic implementation has area O + N), which is the best possible.

Keywords

Binary division; VLSI; cellular array; chip layout; circuit design; combinational logic; hardware divider; integer arithmetic; logic design; systolic array; Computer science; Hardware; Joining processes; Logic arrays; Logic design; Mathematics; Nearest neighbor searches; Systolic arrays; Very large scale integration; Wires; Binary division; VLSI; cellular array; chip layout; circuit design; combinational logic; hardware divider; integer arithmetic; logic design; systolic array;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.1987.1676952

Filename

1676952