Power and Area Optimization for Run-Time Reconfiguration System On Programmable Chip Based on Magnetic Random Access Memory

Author

Zhao, Weisheng ; Belhaire, Eric ; Chappert, Claude ; Mazoyer, Pascale

Author_Institution

CNRS, Univ. Paris Sud, Paris

Volume

45

Issue

2

fYear

2009

Firstpage

776

Lastpage

780

Abstract

In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 nm design kit and a complete magnetic tunnel junction model.

Keywords

MRAM devices; circuit optimisation; field programmable gate arrays; low-power electronics; magnetic tunnelling; system-on-chip; FPGA; MRAM; SOPC; STMicroelectronics design kit; field programmable gate arrays; magnetic random access memory; magnetic tunnel junction model; run-time reconfiguration system; size 90 nm; switching circuit; system-on-programmable chip; FPGA; Flip-flop; LUT; MRAM; SOPC; low power and low die area; nonvolatile; run-time reconfiguration;

fLanguage

English

Journal_Title

Magnetics, IEEE Transactions on

Publisher

ieee

ISSN

0018-9464

Type

jour

DOI

10.1109/TMAG.2008.2006872

Filename

4782120