An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions

Author

Murakawa, Masahiro ; Adachi, Toshio ; Niino, Yoshihiro ; Kasai, Yuji ; Takahashi, Eiichi ; Takasuka, Kaoru ; Higuchi, Tetsuya

Author_Institution

Adv. Semicond. Res. Center, Nat. Inst. of Adv. Ind. Sci. & Technol., Ibaraki, Japan

Volume

38

Issue

3

fYear

2003

fDate

3/1/2003 12:00:00 AM

Firstpage

495

Lastpage

502

Abstract

We have developed a large-scale integration (LSI) for Gm-C intermediate frequency (IF) filters, attaining a 63% reduction in filter area, a 26% reduction in power dissipation, compared with existing commercial products using the same process technology and filter topology, and a yield rate of 97%. The developed chip is calibrated within a few seconds by a genetic algorithm - an efficient AI technique for difficult optimization problems. Our calibration method, which can be applied to a wide variety of analog circuits, leads to cost reductions and the efficient implementation of analog LSIs.

Keywords

CMOS analogue integrated circuits; active filters; calibration; cascade networks; circuit optimisation; genetic algorithms; integrated circuit testing; integrated circuit yield; large scale integration; low-power electronics; 440 to 470 kHz; AI-calibrated IF filter; Gm-C intermediate frequency filters; analog LSIs; analog circuits; area reduction; cascaded sixth-order cells; chip calibration; double-poly double-metal N-CMOS process; filter area; filter topology; frequency response; genetic algorithm; large-scale integration; optimization problems; power dissipation reduction; yield enhancement method; yield rate; Analog circuits; Artificial intelligence; Calibration; Circuit topology; Costs; Filters; Frequency; Genetic algorithms; Large scale integration; Power dissipation;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.808303

Filename

1183858