Design and performance testing of a 2.29-GB/s Rijndael processor

Author

Verbauwhede, Ingrid ; Schaumont, Patrick ; Kuo, Henry

Author_Institution

Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA

Volume

38

Issue

3

fYear

2003

fDate

3/1/2003 12:00:00 AM

Firstpage

569

Lastpage

572

Abstract

This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mW of power consumption in a 0.18-μm CMOS standard cell technology. This integrated circuit implements the Rijndael encryption algorithm, at any combination of block lengths (128, 192, or 25 bits) and key lengths (128, 192, or 256 bits). We present the chip architecture and discuss the design optimizations. We also present measurement results that were obtained from a set of 14 test samples of this chip.

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; cryptography; 0.18 micron; 2.29 GB/s; 25 to 256 bit; 56 mW; AES compliant encryption chip; Advanced Encryption Standard; CMOS standard cell technology; Rijndael processor; block lengths; chip architecture; design optimizations; encryption throughput; key lengths; power consumption; secret key cryptography; Application specific integrated circuits; CMOS technology; Circuit testing; Clocks; Cryptography; Design optimization; Energy consumption; Integrated circuit technology; Throughput; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.808300

Filename

1183877