• DocumentCode
    1157314
  • Title

    Multimode clock generation using delay-locked loop

  • Author

    Susplugas, O. ; Philippe, P.

  • Author_Institution
    Adv. Dev. Group, Philips Semicond., Caen, France
  • Volume
    39
  • Issue
    4
  • fYear
    2003
  • fDate
    2/20/2003 12:00:00 AM
  • Firstpage
    347
  • Lastpage
    349
  • Abstract
    A design of a programmable frequency synthesiser based on an analogue delay-locked loop and the achieved die are presented. It can be used for clocking a digital-to-analogue converter. The results fit well with the depicted theory.
  • Keywords
    delay lock loops; digital-analogue conversion; frequency synthesizers; programmable circuits; timing circuits; DAC clocking; analogue DLL; analogue delay-locked loop; digital-to-analogue converter; multimode clock generation; programmable frequency synthesiser;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20030268
  • Filename
    1184058
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1157314