Semisystolic incremental realization of FIR digital filters using ternary arithmetic

A fully incremental realization of finite impulse response (FIR) filters is presented in which ternary, incremental representations are used for all the signals in the structure and the impulse response. Delta modulation (DM) is used for this purpose, allowing a considerable simplification of the arithmetic involved in the filtering operations. Simulation showed that the proposed DM-adder has lower mean-square error (MSE) and reduced processing delay with respect to existing DM-adders, while demonstrating the feasibility of the proposed modular incremental realization for FIR filters