DocumentCode
1166842
Title
Distributed Differential Oscillators for Global Clock Networks
Author
Chan, Steven C. ; Shepard, Kenneth L. ; Restle, Phillip J.
Author_Institution
Dept. of Electr. Eng., Columbia Univ., New York, NY
Volume
41
Issue
9
fYear
2006
Firstpage
2083
Lastpage
2094
Abstract
This paper presents a distributed differential oscillator global clock network where the clock capacitance is rendered resonant with a set of on-chip spiral inductors. The clock amplitude and clock phase are both uniform across the entire global distribution, making this design scalable and compatible with existing local clocking methodologies. The resonant network, combined with phase averaging of the distributed oscillator, provides high immunity to process-, voltage-, and temperature-variation-induced timing uncertainty. Measurement results from a prototype design implemented in a 0.18-mum CMOS technology show almost an order of magnitude less jitter and power than a traditional tree-driven grid global clock distribution. On-chip measurement circuits are used to characterize the jitter on the test chip, while a simulation model is used to examine skew and higher-order resonances in the resonant clock network
Keywords
CMOS integrated circuits; clocks; jitter; oscillators; 0.18 micron; CMOS technology; clock capacitance; distributed differential oscillators; global clock networks; local clocking methodologies; on-chip measurement circuits; on-chip spiral inductors; resonant clock network; resonant network; CMOS technology; Capacitance; Circuit testing; Clocks; Jitter; Network-on-a-chip; Oscillators; Resonance; Semiconductor device measurement; Spirals; Clock distribution; inductance; jitter; resonant clocking; skew; timing circuits;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2006.880610
Filename
1683900
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