DocumentCode
1166902
Title
A 100-dB SFDR 80-MSPS 14-Bit 0.35- 
BiCMOS Pipeline ADC
Author
Bardsley, Scott ; Dillon, Christopher ; Kummaraguntla, Ravi ; Lane, Charles ; Ali, Ahmed M A ; Rigsbee, Baeton ; Combs, Darren
Author_Institution
Analog Devices, Greensboro, NC
Volume
41
Issue
9
fYear
2006
Firstpage
2144
Lastpage
2153
Abstract
This paper describes a 14-bit 80-MSPS ADC with 100-dB SFDR at 70-MHz input frequency in a 0.35-mum single-well BiCMOS technology drawing 1.2 W from a dual 3.3 V/5.0 V supply. Key barriers to high dynamic range in pipeline ADCs at high clock rates and some methods to overcome these barriers will be presented. These methods include a sampling front-end without the use of a designated Sample and Hold (S/H). A BiCMOS switching input buffer is used along with the strategic use of BiCMOS design techniques. Also, calibration is combined with capacitor shuffling to maximize linearity with minimal noise impact
Keywords
BiCMOS integrated circuits; analogue-digital conversion; buffer circuits; integrated circuit design; 0.35 micron; 1.2 W; 14 bit; 3.3 V; 5.0 V; 70 MHz; BiCMOS pipeline ADC; BiCMOS switching input buffer; analog-to-digital converter; capacitor shuffling; single-well BiCMOS technology; spurious free dynamic range; Acoustical engineering; BiCMOS integrated circuits; Calibration; Capacitors; Clocks; Dynamic range; Frequency; Linearity; Pipelines; Sampling methods; Analog-to-digital converter (ADC); boost; bootstrap; capacitor shuffling; comparator; flash; high speed; input buffer; latching comparator; pipeline; switched capacitor;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2006.880590
Filename
1683906
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