VLSI Block Placement With Alignment Constraints

Author

Chen, Song ; Dong, Sheqin ; Hong, Xianlong ; Ma, Yuchun ; Cheng, C.K.

Author_Institution

Dept. of Comput. Sci., Tsinghua Univ., Beijing

Volume

53

Issue

8

fYear

2006

Firstpage

622

Lastpage

626

Abstract

Corner block list (CBL) is a room-based floorplan representation. In this brief, we give a sufficient and necessary condition for the feasibility of a CBL, and we also deal with alignment constraints in CBL. A method is proposed to identify topological relation between two blocks in CBL. Based on the topological relations between blocks, it is also found that a sufficient and necessary condition to judge whether or not a CBL is feasible under alignment constraints. The experimental results showed the efficiency and effectiveness of the proposed method

Keywords

VLSI; circuit complexity; circuit optimisation; integrated circuit layout; VLSI; alignment constraints; block placement; corner block list; floorplan representation; topological relations; Analog circuits; Circuit simulation; Computer science; Integrated circuit interconnections; Integrated circuit technology; Simulated annealing; Smoothing methods; Space technology; Stochastic processes; Very large scale integration; Alignment; corner block list (CBL); floorplanning; placement;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2006.876374

Filename

1683968