Patents [Method of manufacturing semiconductor devices - US Patent No. 3,025,589]

Two pages of Jean Hoerni\´s 1962 US Patent No. 3,025,589 are reproduced: the first page of diagrams and the first page of claims. J. Hoerni of Fairchild Semiconductor was issued the patent for what is now known as "the planar process" for making npn transistors, with all parts interconnected on one plane by a layer of oxide. His work was crucial to Noyce and Kilby\´s development of the integrated circuit (IC).