DocumentCode
117084
Title
Power efficient priority encoder and decoder
Author
Singha, Thockchom Birjit ; Konwar, Sharmila ; Roy, Sandip ; Vanlalchaka, Reginald H.
Author_Institution
Dept. of Electron. & Commun. Eng., Tezpur Univ., Tezpur, India
fYear
2014
fDate
3-5 Jan. 2014
Firstpage
1
Lastpage
5
Abstract
The main aim of VLSI designers being low power design, this paper presents a CMOS-based new design approach for a low power adiabatic 4:2 Priority Encoder and a 2:4 Decoder. The proposed designs are compared with the standard adiabatic logic styles- PFAL, ECRL and 2n2n2p, revealing lesser power consumption. The simulation is carried out in NI-Multisim software at 0.5 μm CMOS technology for frequency range 200MHz - 800MHz.
Keywords
CMOS integrated circuits; VLSI; circuit simulation; decoding; encoding; low-power electronics; CMOS technology; ECRL; NI-Multisim software; PFAL; VLSI; decoder; frequency 200 MHz to 800 MHz; low power design; power consumption; priority encoder; size 0.5 mum; CMOS integrated circuits; Computers; Decoding; Logic gates; Power dissipation; Standards; Transistors; 2n2n2p; Adiabatic logic; ECRL; PFAL; decoder; power dissipation; power saving; priority encoder;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Communication and Informatics (ICCCI), 2014 International Conference on
Conference_Location
Coimbatore
Print_ISBN
978-1-4799-2353-3
Type
conf
DOI
10.1109/ICCCI.2014.6921806
Filename
6921806
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