A universal test set for CMOS circuits

Author

Gupta, Gopal ; Jha, Niraj K.

Author_Institution

SILC Technol., Waltham, MA, USA

Volume

7

Issue

5

fYear

1988

fDate

5/1/1988 12:00:00 AM

Firstpage

590

Lastpage

597

Abstract

A universal test set for CMOS circuits is demonstrated that can be derived from the functional description of the circuit alone. It is shown that for a restricted class of CMOS circuits, the gate-level universal test set (UTS_g) consisting of maximal false vectors and minimal true vectors can sensitize every detectable stuck-open fault in the circuit. A universal initialization set (UIS) is defined which can also be derived from just the functional description, and which contains initialization vectors for each of the test vectors. This set consists of maximal true vectors and minimal false vectors. It is shown that a test set on UTS_g and UIS can be guaranteed to detect every detectable stuck-open fault in both redundant and irredundant CMOS implementation of the function, even in the presence of arbitrary delays and timing-skews. The size of the test set is also investigated

Keywords

CMOS integrated circuits; integrated circuit testing; logic testing; CMOS circuits; IC testing; gate-level universal test set; initialization vectors; irredundant; logic testing; maximal false vectors; maximal true vectors; minimal false vectors; minimal true vectors; redundant; stuck-open fault; universal initialization set; universal test set; CMOS process; CMOS technology; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Inverters; Large-scale systems; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.3197

Filename

3197